1. Field of the Invention
This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing semiconductor devices having contact holes of different sizes via which the wirings thereof are made.
2. Description of the Related Art
It is known in the art that a semiconductor integrated circuit is formed to have first and second wiring patterns which are laminated over a semiconductor substrate and are isolated from each other by means of an interlayer insulation film. The first wiring pattern is constituted by a plurality of lower wiring layers and the second wiring pattern is constituted by a plurality of upper wiring layers. The upper wiring layers are connected to the lower wiring layers via a plurality of contact holes formed in the interlayer insulation film. Each contact hole is formed in an area in which one set of upper and lower wiring layers connected to each other via the contact hole overlap each other. The sizes of the contact holes may vary depending on the withstand current determined for each contact hole. However, the matching margin A between the contact hole and the lower wiring layer and the matching margin B between the contact hole and the upper wiring layer are constant. The matching margin A is determined depending on an aligning error of a mask pattern used in a process for forming the first wiring pattern, and the matching margin B is determined depending on an aligning error of mask patterns used in processes for forming the contact hole and the first wiring pattern.
The above semiconductor integrated circuit can be formed at relatively high yield when the integration density is low. However, if the width of the wiring is narrowed with an increase in the integration density and the size C of the contact hole is set, for example, to be less than 1.5 .mu.m according to the width of the wiring, the manufacturing yield of the semiconductor integrated circuit is considerably lowered.